This review covers our recent (2005–2010) experiments and modeling-simulation work dedicated to the evaluation of natural radiation-induced soft errors in advanced static memory (SRAM) technologies. The impact on the chip soft-error rate (SER) of both terrestrial neutrons induced by cosmic rays and alpha-particle emitters, generated from traces of radioactive contaminants in CMOS process or packaging materials, has been experimentally investigated by life (i.e. real-time) testing performed at ground level on the Altitude Single-event Effect Test European Platform (ASTEP) and underground at (...)

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This chapter briefly surveys different aspects of the ASTEP/LSM program, including the description of the two test platforms and their radiation environment, the real-time setups and a synthesis of more than one cumulative year of real-time characterization concerning two generations of SRAM circuits manufactured in 130 and 65 nm CMOS technologies.
This book chapter will be published in Radiation Effects in Semiconductors (ISBN: 9781439826942) Editor(s): Krzysztof Iniewski, CMOS Emerging Technologies Inc., Vancouver, British Columbia
See the CRC Press web page for this book (...)

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The Plateau de Bure ASTEP Platform Test in natural radiation environment of electronic components and circuits
J.L. Autran, D. Munteanu, S. Sauze Institut Matériaux Microélectronique Nanosciences de Provence (IM2NP, UMR CNRS 6242) Aix-Marseille Université et Centre National de la Recherche Scientifique
P. Roche, G. Gasiot Groupe Radiations, Recherche et Développement Central, STMicroelectronics-Crolles
J. Borel JB R&D, Saint-Etienne en Dévoluy
Abstract - Reducing the size of microelectronic devices and increasing the integration density of circuits lead (following the famous Moore’s law) to (...)

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After the success of the first edition, RADSOL 2009 will be held in Paris, CNRS Campus "Michel-Ange" on June 25-26, 2009.
This national workshop (in French) will address the growing influence of the radiative natural constraint on the reliability of electronic systems.
This two-days seminar is designed for payers, designers and systems integrators (motor transport, rail transport, computers, data processing) and offers a review of methods of evaluation and testing of the effects of natural radiation on the reliability of components and systems.
Visit the website of RADSOL 2009: (...)

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Abstract— We report real-time SER characterization of CMOS 65nm SRAM memories in both altitude and underground environments. Neutron and alpha-particle SERs are compared with data obtained from accelerated tests and values previously measured for CMOS 130nm technology.
Index Terms— Single-Event Rate (SER), real-time testing, atmospheric neutrons, terrestrial radiation environment, static memory, accelerated tests, SER simulation, alpha contamination, neutron-induced SER.
Paper presented at RADECS 2008, the 2008 European Workshop on Radiation Effects on Components and Systems, 10th to 12th (...)

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Abstract— This work reports real-time soft-error rate (SER) testing of semiconductor static memories in both altitude and underground environments to separate the component of the SER induced by the cosmic rays (i.e. primarily by atmospheric neutrons) from that caused by on-chip radioactive impurities (alpha-particle emitters). Two European dedicated sites were used to perform long-term real-time measurements with the same setup: the Altitude SEE Test European Platform (ASTEP) at the altitude of 2252m and the underground laboratory of Modane (LSM, CEA-CNRS) under 1700 m of rock (4800 (...)

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Abstract - The “Altitude SEE Test European Platform” (ASTEP ) is dedicated to real-time soft-error rate (SER) testing of semiconductor memories. The platform, located in the French Alps on the “Plateau de Bure” at 2552m, has been operational since March 2006. This test facility includes a proprietary automatic test equipment specially designed for static memory (SRAM) testing and secured remote control operation via internet. Real-time SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-time and accelerated SER. (...)

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Abstract— The “Altitude SEE Test European Platform” (ASTEP) is dedicated to real-time soft-error rate (SER) testing of semiconductor memories. The platform, located in the French Alps on the “Plateau de Bure” at 2552m, has been operational since March 2006. This test facility includes a proprietary automatic test equipment specially designed for static memory (SRAM) testing and secured remote control operation via internet. First real-time SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-time and accelerated SER. (...)

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Abstract— The “Altitude SEE Test European Platform” (ASTEP) is dedicated to real-time soft-error rate (SER) testing of semiconductor memories. The platform, located in the French Alps on the “Plateau de Bure” at 2552m, has been operational since March 2006. This test facility includes a proprietary automatic test equipment specially designed for static memory (SRAM) testing and secured remote control operation via internet. First real-life SER measurements on 3.6 Gbit of SRAMs manufactured in CMOS 130 nm technology are reported, as well as the comparison between real-life and accelerated SER. (...)

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